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summit microelectronics, inc. ? 300 orchard city drive, suite 131 ? campbell, ca 95008 ? telephone 408-378- 6461 ? fax 408-378-6586 ? www.summitmicro.com 1 s93vp662/s93vp663 ? summit microelectronics, inc. 1998 2019 1.1 5/15/98 characteristics subject to change without notice summit microelectronics, inc. features ? voltage protection? ? precision low-v cc write lockout ? all write operations inhibited when v cc falls below v lock ? one 3volt and two 5volt system versions Cv lock = 2.6v+.1v/-.05v Cv lock = 4.25v +.25v/-0.0v Cv lock = 4.50 +.25v/-0.0v ? 100% compatible with industry standard microwire devices ? 1,000,000 program/erase cycles ? 100 year data retention ? commercial industrial temperature range overview the s93vp662 and s93vp663 are 4k-bit serial e 2 prom memories integrated with a precision v cc sense circuit. the sense circuit will disable write opera- tions whenever v cc falls below the v lock voltage. they are fabricated using summits advanced cmos e 2 prom technology and is suitable for both 3 and 5 volt systems. both devices have 4k-bits of e 2 prom memory that is accessible via the industry standard microwire bus. the s93vp662 is configured with an internal org pin tied low providing an 8-bit byte organization and the s93vp663 is configured with an internal org pin tied high providing a 16-bit word organization. both the s93vp662 and s93vp663 have page write capability. the devices are designed for a minimum 1,000,000 program/erase cycles and have data retention in ex- cess of 100 years. block diagram 4k serial e 2 prom with a precision low-v cc lockout circuit + - 8 cs di do sk 1 2 3 4 5 gnd 2019 ill2 1.0 memory array 4k-bit e 2 prom write control address decoder mode decode data i/o reset control reset pulse generator 5khz oscillator v trip 1.26v v cc
2 s93vp662/s93vp663 2019 1.1 5/15/98 pin functions pin name function cs chip select sk clock input di serial data input do serial data output v cc +2.7 to 6.0v power supply gnd ground pin configuration dip package (p) soic package (s) device operation applications the s93vp662/vp663 was designed specifically for applications where the integrity of the stored data is paramount. in recent years, as the operating voltage range of serial e 2 proms has widened, most semicon- ductor manufacturers have arbitrarily eliminated their v cc sense circuits. the s93vp662/vp663 will protect your data by guaranteeing write lockout below the se- lected v cc lockout voltage. v cc lockout the s93vp662/vp663 has an on-board precision v cc sense circuit. whenever v cc is below v lock , the s93vp662/vp663 will disable the internal write circuitry. the v cc lockout circuit will ensure a higher level of data integrity than can be expected from industry standard devices that have either a very loose specification or no v cc lockout specification. during a power-on sequence all writes will be inhibited below the v lock level and will continue to be held in a write inhibit state for approximately 200ms after v cc reaches, then stays at or above v lock . the 200ms delay provides a buffer space for the microcontroller to com- plete its power-on initialization routines (reading is ok) while still protecting against inadvertent writes. during a power-down sequence initiation of writes will be inhibited whenever v cc falls below v lock . this will guard against the systems microcontroller performing an inadvertent write within the danger zone. (see an003) general operation the s93vp662/vp663 is a 4096-bit nonvolatile memory intended for use with industry standard microproces- sors. the s93vp663 is organized as x16, seven 11-bit instructions control the reading, writing and erase operations of the device. the s93vp662 is organized as x8, seven 12-bit instructions control the reading, writing and erase operations of the device. the device operates on a single 3v or 5v supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance 2019 ill1 1.0 cs sk di do v cc nc nc gnd 1 2 3 4 8 7 6 5 cs sk di do v cc nc nc gnd 1 2 3 4 8 7 6 5
3 s93vp662/s93vp663 2019 1.1 5/15/98 state during chip select by shifting a dummy 1 into the di pin. the do pin will enter the high impedance state on the falling edge of the clock (sk). placing the do pin into the high impedance state is recommended in appli- cations where the di pin and the do pin are to be tied together to form a common di/o pin. the format for all instructions is: one start bit; two op code bits and either eight (x16) or nine (x8) address/ instruction bits. read upon receiving a read command and an address (clocked into the di pin), the do pin of the s93vp662/ vp663 will come out of the high impedance state and, will first output an initial dummy zero bit, then begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ). write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start automatic erase and write cycle to the memory location specified in the instruction. the ready/busy status of the s93vp662/vp663 can be determined by selecting the device and polling the do pin. erase upon receiving an erase command and address, the cs (chip select) pin must be deslected for a minimum of 250ns (t csmin ). the falling edge of cs will start the auto erase cycle of the selected memory location. the ready/busy status of the s93vp662/vp663 can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical 1 state. figure 1. sychronous data timing figure 2. read instruction timing sk 2019 ill 3 1.0 di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data v alid t sklow sk 2019 ill4 1.0 cs di do t cs standby t hz high-z high-z 11 0 a n a n? a 0 0 d n d n? d 1 d 0 t pd0
4 s93vp662/s93vp663 2019 1.1 5/15/98 erase/write enable and disable the s93vp662/vp663 powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write in- struction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all s93vp662/vp663 write and clear instructions, and will prevent any accidental writing or clearing of the device. data can be read normally from the device regardless of the write enable/disable status. erase all upon receiving an eral command, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the s93vp662/vp663 can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical 1 state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of 250ns (t csmin ). the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/ busy status of the s93vp662/vp663 can be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral command is executed. figure 3. write instruction timing figure 4. erase instruction timing sk 2019 ill 5 1.0 cs di do t cs standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew sk 2019 ill6 1.0 cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0
5 s93vp662/s93vp663 2019 1.1 5/15/98 figure 5. ewen/ewds instruction timing figure 6. eral instruction timing sk 2019 ill 7 1.0 cs di standby 10 0 * * enable=1 1 disable=00 sk 2019 ill 8 1.0 cs di do t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00 standby
6 s93vp662/s93vp663 2019 1.1 5/15/98 figure 7. wral instruction timing sk 2019 ill 10 1.0 cs di do t cs high-z 10 1 busy ready status verify t sv t hz t ew 0 0 standby d o d n instruction set instruction start opcode address data comments bit s93vp662 s93vp663 s93vp662 s93vp663 read 1 10 a8Ca0 a7Ca0 read address anCa0 erase 1 11 a8Ca0 a7Ca0 clear address anCa0 write 1 01 a8Ca0 a7Ca0 d7Cd0 d15Cd0 write address anCa0 ewen 1 00 11xxx xxxx 11xxx xxx write enable ewds 1 00 00xxx xxxx 00xxx xxx write disable eral 1 00 10xxx xxxx 10xxx xxx clear all addresses wral 1 00 11xxx xxxx 01xxx xxx d7Cd0 d15Cd0 write all addresses 2019 pgm t5 1.0
7 s93vp662/s93vp663 2019 1.1 5/15/98 d.c. operating characteristics v cc = +2.7v to +6.0v, unless otherwise specified. t a = -40oc to +85oc limits symbol parameter min. typ. max. units test conditions i cc power supply current 3 ma di = 0.0v, f sk = 1mhz (operating) v cc = 5.0v, cs = 5.0v, output open i sb power supply current 50 m a cs = 0v (standby) i li input leakage current 2 m av in = 0v to v cc i lo output leakage current 10 m av out = 0v to v cc , (including org pin) cs = 0v v il1 input low voltage -0.1 0.8 v 4.5v v cc <5.5v v ih1 input high voltage 2 v cc +1 v v il2 input low voltage 0 v cc x0.2 v 1.8v v cc <2.7v v ih2 input high voltage v cc x0.7 v cc +1 v v ol1 output low voltage 0.4 v 4.5v v cc <5.5v v oh1 output high voltage 2.4 v i ol = 2.1ma i oh = -400 m a v ol2 output low voltage 0.2 v 1.8v v cc <2.7v v oh2 output high voltage v cc -0.2 v i ol = 1ma i oh = -100 m a note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. 2019 pgm t3 1.0 absolute maximum ratings* temperature under bias ................. C55 c to +125 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to ground (1) ............ C2.0v to +v cc +2.0v v cc with respect to ground ............... C2.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100 ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter min. max. units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 2019 pgm t2 1.1
8 s93vp662/s93vp663 2019 1.1 5/15/98 a.c. characteristics limits v cc =2.7v-4.5v v cc =4.5v-5.5v test symbol parameter min. max. min. max. units conditions t css cs setup time 100 50 ns t csh cs hold time 0 0 ns v il = 0.45v t dis di setup time 200 100 ns v ih = 2.4v t dih di hold time 200 100 ns c l = 100pf t pd1 output delay to 1 0.5 0.25 m sv ol = 0.8v t pd0 output delay to 0 0.5 0.25 m sv oh = 2.0v t hz (1) output delay to high-z 200 100 ns t ew program/erase pulse width 10 10 ms t csmin minimum cs low time 0.5 0.25 m s t skhi minimum sk high time 0.5 0.25 m s t sklow minimum sk low time 0.5 0.25 m s t sv output delay to status valid 0.5 0.25 m sc l = 100pf sk max maximum clock frequency dc 500 dc 1000 khz note: (1) this parameter is tested initially and after a design or process change that affects the parameter. c l = 100pf 2019 pgm t6 1.0 note: (1) this parameter is tested initially and after a design or process change that affects the parameter. pin capacitance symbol test max. units conditions c out (1) output capacitance (do) 5 pf v out =ov c in (1) input capacitance (cs, sk, di, org) 5 pf v in =ov 2019 pgm t4 1.0
9 s93vp662/s93vp663 2019 1.1 5/15/98 figure 8. v lock timing diagram t puw t glitch t ldly v lock v cc t puw t ldly v lockout v lockout v lockout internal action 2019 ill9 1.0 s24vp662/vp663-2.7 s24vp662/vp663Ca s24vp662/vp663Cb symbol parameter min max min max min max unit v lock write lockout voltage level 2.55 2.70 4.25 4.50 4.50 4.75 v t puw power-up write delay 130 20 130 270 130 270 ms t ldly delay to v lockout 555 m s t glitch glitch filter 30 30 30 ns v lock circuit ac and dc electrical characteristics t a = -40 c to +85 c 2019 pgm t1 1.3
10 s93vp662/s93vp663 2019 1.1 5/15/98 .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic ill.2 .375 (9.525) pin 1 indicator .015 (.381) min. .130 (3.302) .100 (2.54) typ. .018 (.457) typ. .060 .005 (1.524) .127 typ. .130 (3.302) seating plane .070 (1.778) .0375 (0.952) .300 (7.620) 5 -7 typ. (4 plcs) .350 (8.89) .009 .002 (.229 .051) 0 -15 .250 (6.350) 8pn pdip/p ill.3 8 pin soic (type s) package jedec (150 mil body width) 8 pin pdip (type p) package
11 s93vp662/s93vp663 2019 1.1 5/15/98 ordering information operating temperature range blank = 0 c to +70 c i = -40 c to +85 c package p = 8 lead pdip s = 8 lead soic tape and reel option te7 = 7 inch reel, 500 units/reel te13 = 13 inch reel, 2000 units/reel operating voltage range a = 4.5v to 5.5v v lock min @4.25v b = 4.5v to 5.5v v lock min @4.50v 2.7 = 2.7v to 5.5v v lock min @2.55v s93vpxx p i -2.7 te7 base part number s93vp662 = 8-bit data configuration s93vp663 = 16-bit data configuration 2019 ill11 1.1
12 s93vp662/s93vp663 2019 1.1 5/15/98 notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to impr ove design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits describ ed herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a users specific application. while the information in this publication has been carefully checked, summit microelectronics, i nc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect it s safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives writte n assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 1998 summit microelectronics, inc.

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